1. Field of the Invention
The present invention relates to a flat panel display and, more particularly, to an active matrix organic light emitting device capable of avoiding a defective element and improving picture quality by reducing a taper angle of a substrate surface.
2. Background of the Invention
In general, pixels in an active matrix organic light emitting device (AMOLED) are arranged on the substrate in a matrix form. Each pixel includes an electroluminescence (EL) element, where an anode electrode, an organic thin film layer, and a cathode electrode are stacked, and a thin film transistor (TFT) as an active element connected to the EL element for driving the EL element.
FIG. 1A shows a cross-sectional view of a conventional bottom-emitting OLED. Referring to FIG. 1A, a buffer layer 105 is formed on an insulating substrate 100, and source and drain regions 111 and 115 of a semiconductor layer 110 are formed on the buffer layer 105. A gate 125 is formed on a gate insulating layer 120, and source and drain electrodes 141 and 145 are formed on an inter-layer insulating layer 130 through contact holes 131 and 135 to be connected to the source and drain regions 111 and 115, respectively. As a result, the TFT is fabricated. Wiring 147, such as a data line or a power supply line, is formed on the inter-layer insulating layer 130.
An anode electrode 170, as a lower electrode connected to the drain electrode 145 through a via hole 155, is formed on a passivation layer 150, and an organic thin film layer 185 and a cathode electrode 190, as an upper electrode, are formed on the insulating substrate 100, thereby fabricating the organic EL element.
FIG. 1B shows a detailed cross-sectional view of the red on R pixel EL element within an emission region of an R pixel in the OLED of FIG. 1A. A method for fabricating the EL diode is described in detail below, with reference to FIG. 1B. A cleaning process is performed after forming the anode electrode 170 connected to the drain electrode 145 of the TFT through the via hole 155. A 600 Å thick hole injecting layer 185a is then formed with CuPc on the substrate using a vacuum deposition method, and a 300 Å thick hole transporting layer 185b is formed with NPB on the hole injecting layer 185a. A 200 Å thick Alq+DCM is deposited on the hole transporting layer 185b to form a red color emission layer 185c. A 200 Å thick Alq3 is formed on the red color emission layer 185c to form an electron transporting layer 185d, thereby forming the organic thin film layer 185. Finally, a LiF/Al, as the cathode electrode 190, is deposited by a thermal evaporation method. Although not shown in the figure, a hole blocking layer may be formed between the red color emission layer 185c and the electron transporting layer 185d, or an electron injecting layer may be formed on the electron transporting layer 185d. 
After forming the organic thin film layer 185 and the cathode electrode 190 on the anode electrode 170, as shown in FIG. 1B, a sealant (not shown) is applied on the insulating substrate 100, and an encapsulating substrate is bonded to the insulating substrate 100 to prevent external oxygen and moisture from being introduced inside, thereby fabricating the conventional OLED.
The conventional OLED having the above mentioned structure may have pinhole defects occurring near a stepped portion of the anode electrode 170, near the via hole 155 and near the contact holes 131 and 135, and/or short-circuit defects between the anode electrode 170 and the cathode electrode 190. Furthermore, portions where the organic emission layer 185c is not deposited or not uniformly deposited may be thinner than other portions near the stepped portion of the anode electrode 170 and near the contact holes 131 and 135 and via holes 155. When a high voltage is applied between the anode electrode 170 and the cathode electrode 190, a current density may focus on the portion where the organic emission layer 185c is not deposited or is thinly deposited, so that one or more spherical dark spot may occur. As a result, the emission region may decrease and the picture quality may deteriorate due to the occurrence of the dark spot.
Oxygen and/or moisture may be more easily introduced through a portion where the cathode electrode 190 is not densely formed. When a high voltage is applied between the anode electrode 170 and the cathode electrode 190, a current density is focused on the portion where the cathode electrode 190 is not densely formed, and a void occurs in the cathode electrode 190 due to an electromigration. Heat may occur due to increased resistance from an external oxygen inflow. As a result, a spherical dark spot may occur in the portion as time passes.
To prevent defects, such as a short-circuit or the dark spot, a contact hole or via hole may be formed having a small taper angle. However, there has been a limit in reducing the taper angle of the contact hole or via hole due to difficulties in design of a high resolution flat panel display.
U.S. Pat. No. 5,684,365 discloses a technique that limits a taper angle of a passivation layer at an edge of an opening for exposing some portions of the anode electrode. FIG. 2 illustrates a cross-sectional view of a conventional bottom-emitting OLED. Referring to FIG. 2, a buffer layer 205 is formed on an insulating substrate 200, and a semiconductor layer 210 having source and drain regions 211 and 215 is formed on the buffer layer 205. A gate 225 is formed on a gate insulating layer 220, and source and drain electrodes 241 and 245 are formed to be connected to the source and drain regions 211 and 215, respectively, through contact holes 231 and 235 on an inter-layer insulating layer 230. In this case, an anode electrode 270, as a lower electrode to be connected to the drain electrode 245, is formed on the inter-layer insulating layer 230.
After depositing a passivation layer 250, at a thickness of 0.5 to 1.0 μm formed of an insulating layer, such as an silicon nitride layer, on a substrate 200, the passivation layer 250 is etched to form an opening 275 exposing some portions of the anode electrode 270. In this case, the passivation layer 250 is formed to have a taper angle of 10 to 30° with respect to the anode electrode 270 at an edge of the opening 275. An organic thin film layer 285 and a cathode electrode 290 as an upper electrode are then formed on the substrate 200. The organic thin film layer 285 has at least one of a hole injecting layer, a hole transporting layer, an R, G, or B emission layer, a hole barrier layer, an electron transporting layer, or an electron injecting layer, as shown in FIG. 1B.
U.S. Pat. No. 6,246,179 discloses a technique that uses an organic insulating layer having a planarizing function to prevent defects from occurring near a via hole or a contact hole and at a stepped portion. FIG. 3 shows a cross-sectional view of the OLED having a conventional top-emitting structure. Referring to FIG. 3, a buffer layer 305 is formed on an insulating substrate 300, and a semiconductor 310, having source and drain regions 311 and 315, is then formed on the buffer layer 305. A gate 325 is formed on a gate insulating layer 320, and source and drain electrodes 341 and 345 are connected to the source and drain regions 311 and 315, respectively, through contact holes 331 and 335 on an inter-layer insulating layer 330. In this case, wiring 347, such as a data line or a power supply line, is formed at the same time the source and drain electrodes 341 and 345 are formed on the inter-layer insulating layer 330.
A planarization layer 360 is formed on a passivation layer 350, and an anode electrode 370, as a lower electrode, is connected to one electrode, for example, to the drain electrode 345 between the source and drain regions 341 and 345 through the via hole 355 on the planarization layer 360. A pixel defining layer 365, having an opening 375 for exposing some portions of an anode electrode 370, is formed, and an organic thin film layer 385 and a cathode electrode 390 as an upper electrode are formed on the pixel defining layer 365 and the anode 370. The organic thin film layer 385 has at least one of a hole injecting layer, a hole transporting layer, a R, G, or B emission layer, a hole blocking layer, an electron transporting layer and an electron injecting layer, as shown in FIG. 1B.
As in the above mentioned conventional OLED, a taper angle of the passivation layer connected to the anode electrode within the opening is limited to between 10° to 30°, or a taper angle of the pixel defining layer is limited to between 20° to 80°, thereby preventing defects in the organic emission layer. In addition, the problem of the stepped portion may be solved by using the planarization layer, thereby preventing the defect of the organic emission layer.
However, in the high-resolution OLED, there has been a limit to reducing the taper angle of the passivation layer or the pixel defining layer due to difficulties in the design process. Furthermore, the reliability of the element depends on a taper angle between the pixel defining layer and the anode electrode. When the taper angle is large, the organic emission layer and the cathode electrode easily deteriorate at the edge of the opening. When the taper angle is small, there has been a limit to reducing the tape angle and thickness of the pixel defining layer due to problems of parasitic capacitance and a stepped portion caused by the wiring.
In addition, since the cathode electrode deposited on the entire surface of the substrate is not densely formed near the contact hole, near the via hole and at the stepped portion, as described above, dark spot may occur, or a pinhole or short-circuit defect may occur near the contact hole, near the via hole and at the stepped portion.